Обзор методов описания встраиваемой аппаратуры


Литература - часть 2


Санкт-Петербург, 2004.
  • Z. Navabi. Languages for Design and Implementation of Hardware. The VLSI Handbook—2nd ed. CRC Press, 2007.

  • А.К. Поляков. Языки VHDL и VERILOG в проектировании цифровой аппаратуры. // М.: Солон-Пресс, 2003. 320 с.

  • П.Н. Бибило. Синтез логических схем с использованием языка VHDL. // М.: СОЛОН-Р, 2002. 384 с.

  • Volnei A. Pedroni. Circuit Design with VHDL. // MIT Press, 2004.

  • IEEE Standard VHDL Language Reference Manual. IEEE Std 1076-1987.

  • IEEE Standard Multivalue Logic System for VHDL Model Interoperability. IEEE Std 1164.

  • IEEE Standard VHDL Synthesis Packages. IEEE Std 1076.3-1997.

  • M. Rofoue, Z. Navabi. RT Level Hardware Description with VHDL. The VLSI Handbook—2nd ed. CRC Press, 2007.

  • Weng Fook Lee. Verilog Coding for Logic Synthesis. // John Wiley & Sons, 2003.

  • IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language. IEEE Std 1364-2005.

  • Z. Navabi. Register Transfer Level Hardware Description with Verilog. The VLSI Handbook—2nd ed. CRC Press, 2007.

  • Open SystemC Initiative. .

  • IEEE Standard System C Language Reference Manual. IEEE Std 1666-2005.

  • S. Mirkhani and Z. Navabi. Register-Transfer Level Hardware Description with SystemC. The VLSI Handbook—2nd ed. CRC Press, 2007.

  • Stephen Bailey. Comparison of VHDL, Verilog and SystemVerilog. Model Technology White Paper.

  • Synopsys VCS

  • Mentor Graphics ModelSim. .

  • Cadence NC-Sim.
  • Cadence Incisive Simulators.

  • P. Mishra and N. Dutt. Architecture description languages for programmable embedded systems. // IEEE Proceedings Computers and Digital Techniques., Vol. 152, No. 3, May 2005.

  • W. Qin, and S. Malik. Architecture description languages for retargetable compilation. // The Compiler Design Handbook, CRC Press, 2002.

  • H. Tomiyama, A. Halambi, P. Grun, N. Dutt, A. Nicolau. Architecture Description Languages for Systems-on-Chip Design. // Proc. Asia Pacific Conf. on Chip Design Language, 1999, pp. 109–116.

  • Rainer Leupers.


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